1. Field of the Invention
The invention relates to an asynchronous first in first out (FIFO) interface, and in particular, to an asynchronous FIFO interface in a radio frequency (RF) device.
2. Description of the Related Art
Demand for low cost, low power consumption and smaller radio frequency (RF) receivers of communication systems have increased because the popularity of wireless communications (e.g. cell phones, wireless networks). Additionally, a multitude of devices, such as analog transceivers, digital processors and clock generators have been developed and integrated into a single chip for multifunction ability. For an RF transceiver, analog circuits and digital circuits have different clock requirements. For example, in an analog circuit, a low-jitter clock is required for the analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) to increase the accuracy of data conversion. However, in a digital circuit, the low-jitter clock is not necessary.
In light of the above, the clock of the ADC is separated from the clock of the base band processor in the conventional circuit, as shown in FIG. 1. FIG. 1 is a block diagram of a receiver 100 using an asynchronous FIFO interface. The receiver 100 comprises an RF front-end receiver 110, an ADC 112, a first signal source 114, a FIFO buffer 121, a clock controller 122, a variable integer divider 124, a baseband processor 130, a second signal source 132 and a reference source 140.
The RF front-end receiver 110 receives an RF signal transmitted from a transmitter (not shown in FIG. 1), and converts the RF signal into an intermediate frequency (IF) signal according to an oscillation signal generated by the first signal source 114. The local signal is generated by the first signal source 114 with low-jitter clock to increase the signal-to-noise ratio (SNR) and decrease the blocking effect of the neighboring channels when frequency conversion is performed. The ADC 112 converts the low-IR signal into data (i.e., a digital signal) and outputs the data according to a clock with a variable frequency to avoid the additional use of a low-jitter signal source and meet the demands of the low-jitter clock. The clock with the variable frequency is generated by the variable integer divider 124 according to the local signal from the first signal source 114. The baseband processor 130 performs signal processing of the data, such as transmission mode detection, time-domain data processing, frequency-domain data processing and channel code, according to another oscillation signal generated from the second signal source 132. The second signal source 132 is a fixed-frequency and high jitter signal source, such as ring oscillator which is used to save on hardware costs. The baseband processor 130 operates following the second signal from the second signal source 132. The reference source 140 can be shared by the first signal source 114 and the second signal source 132 to further save on the hardware costs.
The clock (i.e., the second signal) provided from the second signal source 132 to the baseband processor 130 can be asynchronous with the clock provided from each signal source to the ADC 112. Thus, the conventional circuit uses an FIFO interface 120 when processing the asynchronous data transmission between the ADC 112 and the baseband processor 130. The asynchronous FIFO interface 120 comprises a FIFO buffer 121, a clock controller 122 and a variable integer divider 124. The FIFO buffer 121 is coupled between the baseband processor 130 and the ADC 112 to buffer the data transmission between the baseband processor 130 and the ADC 112. The FIFO buffer 121 receives the data from the ADC 112 according to a write clock and outputs the data to the baseband processor 130 according to a readout clock. In this case, the write clock is the clock that operates the ADC 112 (i.e., the clock with the variable frequency from the variable integer divider 124), and the readout clock is the clock that operates the baseband processor 130 (i.e., the second signal from the second signal source 132). When the write clock, operating the ADC 112, is faster than the readout clock, operating the baseband processor 130, the FIFO buffer 121 is in a data-overflow status. Thus, the clock controller 122 increases the divisor of the variable integer divider 124 to decrease frequency of the write clock (i.e., slow down the write clock). On the contrary, when the write clock, operating the ADC 112, is slower than the readout clock, operating the baseband processor 130, the FIFO buffer 121 is in a data-empty status. Thus, the clock controller 122 decreases the divisor of the variable integer divider 124 to increase frequency of the write clock (i.e., speed up the write clock).
In the conventional circuit shown in FIG. 1, the divisor of the variable integer divider 124 is adjusted by the clock controller 122 to control the write clock of the ADC 112 and the data status of the FIFO buffer 112. However, the control of the data status of the FIFO buffer 121 may not need to be adjusted by the variable integer divider 124.